VSP 94x2A
DATA SHEET
2
Table 3–8: I C bus command description, continued
Bit
Name
Description
Subaddress F5 (read only)
D3
D2
D1
D0
LPBLACK
[FP-RGB]
LBD: lower area contains medium brightness level
internal value, only for test purposes
UPBLACK
[FP-RGB]
LBD: upper area contains medium brightness level
internal value, only for test purposes
LPWHITE
[FP-RGB]
LBD: lower area contains high brightness level
internal value, only for test purposes
UPWHITE
[FP-RGB]
LBD: upper area contains high brightness level
internal value, only for test purposes
Subaddress F6h (Read-only, compatible to 940X family)
D7-D5
VERSION
[CP-I2C]
Version Of VSP 94xxX Family:
‘001’: VSP 94x5B
‘010’: VSP 94x2A
‘011’: VSP 94x7B
‘101’: VSP 94x9C
others: reserved
D4
SLS
[CP-I2C]
Line Standard At Device Output
‘0’: 100 Hz (VSP 9402A, VSP 9412A)
‘1’: 50 Hz (VSP 9432A, VSP 9442A)
D3-D1
REV
[CP-I2C]
Revision of VSP94x2A
‘000’: A23 or below
‘001’: A31 or A32
‘010’: B13 or B14
Subaddress FEh
2
FE
Subaddress FFh
FF
Any value to this subaddress executes previous I C protocolls immediately
2
Any value to this subaddress executes previous I C protocolls according to the
take-over-mechanism (dedicated v-pulse, V20, V40, V36)
104
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
