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VSP9407B 参数 Datasheet PDF下载

VSP9407B图片预览
型号: VSP9407B
PDF下载: 下载PDF文件 查看货源
内容描述: PRIMUS强大的扫描速率转换器包括多标准解码器颜色 [PRIMUS Powerful Scan-Rate Converter including Multistandard Color Decoder]
分类和应用: 解码器转换器
文件页数/大小: 126 页 / 1601 K
品牌: MICRONAS [ MICRONAS ]
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VSP 94x2A  
DATA SHEET  
511  
511  
446  
upper headroom  
upper headroom  
442  
white  
black  
256  
144  
64  
0
16  
0
lower headroom  
Fig. 2–2: CVBS, Y and C Amplitude Characteristics.  
When using the sync height based AGC mode, the A/D  
gain increases or decreases depending on the incom-  
ing signal. When using overflow detection only, the  
gain is set to maximum and is reduced whenever an  
’overflow’ occurs.  
2.1.3. Clamping  
The timing of the clamping (pulse) control signals for  
the analog inputs are derived from its corresponding  
CVBS input signal. The clamping algorithm works with  
a split measurement pulse and a clamping pulse. The  
measurement pulse is used to detect the clamping  
error. The clamping pulse is used to enable current  
sources for reducing the detected clamping errors. The  
start and length of the measurement signals are inde-  
pendently adjustable for both channels (CLMPST1,  
CLMPD1, CLMPST2, CLMPD2).  
The signal is low pass filtered so that chrominance and  
noise are not used for detection. The threshold can be  
adjusted by PWTHD. A setting of ’11’ equals 511 and  
means an overflow of the ADC. Other settings react for  
a lower level. The gain only becomes higher when a  
change of the channel is detected or is manually reset  
by AGCRES. AGCFRZE holds the current AGC value.  
The same applies for the clamping signals  
(CLMPST1S, CLMPD1S, CLMPST2S, CLMPD2S).  
Clamping and measurement signals for RGB channel  
are not separate. Clamping for these ADC are con-  
trolled by CLMPST2S and CLMPD2S only. Clamping  
can be suppressed for some lines by CLMPLOW and  
CLMPHIGH to ignore copyprotection information. No  
external sync signals are required.  
A manual setting of the ADCs gain control is possible  
using the parameters AGCADJ1 and AGCADJ2.  
The conversion range (CR) is bigger than the signal  
range (SRY, SRC) leaving a headroom for overshoots  
(see Fig. 2–2).  
.
Gain Control Characteristic  
1.9  
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1
CLMPST1  
CLMPD1  
Measurement ADC1  
Clamping ADC1  
CLMPST1S  
CLMPD1S  
0.9  
0.8  
0.7  
0.6  
0.5  
CLMPST2  
CLMPD2S  
CLMPD2  
Measurement ADC2  
CLMPST1S  
Measurement and Clamping RGBF  
Clamping ADC2  
0
8
16  
24  
32  
40  
48  
56  
64  
AGCADJ1, AGCADJ2 (I²C)  
Fig. 2–3: CVBS ADC Characteristic  
Fig. 2–4: Clamping Signals  
8
Aug. 16, 2004; 6251-552-1DS  
Micronas  
 
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