ADVANCE INFORMATION
VPX 322xE
1.1. System Architecture
The block diagram (Fig. 1–1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YC
b
C
r
samples, adjusts the contrast and brightness,
and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.
Note:
The VPX 322xE is register compatible with the
VPX 322xD family, but not with VPX 3220A, VPX 3216B,
and VPX 3214C family.
RESQ
Clock Gen.
DCO
Sync Processing
HREF
VREF
FIELD
Port
Text Slicer
(not VPX 3224E)
A[7:0]
Adaptive 4H CombFilter
(VPX 3226E only)
MUX
ADC
Video Processing
CVBS/Y
Luma Filter
Y
Y
Video Interface
OEQ
Video Decoder
MUX
Chroma
Demodulator
C
b
C
r
C
b
C
r
Port
B[7:0]
MUX
Chroma
ADC
Line Store
SDA
I2C
SCL
JTAG
PIXCLK
LLC
VACT
TMS
TCK
Fig. 1–1:
Block diagram of the VPX 322xE
Micronas
TDO
TDI
7
MICRONAS [ MICRONAS ]
