VPX 322xE
Contents, continued
Page
46
46
47
49
50
51
53
53
54
54
55
55
56
57
57
57
57
58
59
59
60
60
61
61
62
63
63
63
64
65
66
66
67
67
68
68
71
75
Section
3.
3.1.
3.2.
3.3.
3.4.
3.5.
4.
4.1.
4.2.
4.2.1.
4.2.2.
4.2.3.
4.2.4.
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.7.
4.3.8.
4.3.9.
4.3.10.
4.3.10.1.
5.
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.7.1.
6.
6.1.
6.1.1.
6.1.2.
Title
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Pin Configuration
Pin Circuits
ADVANCE INFORMATION
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Analog Video Input Conditions
Recommended I
2
C Conditions for Low Power Mode
Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI
Recommended Crystal Characteristics
Characteristics
Current Consumption
Characteristics, Reset
XTAL Input Characteristics
Characteristics, Analog Front-End and ADCs
Characteristics, Control Bus Interface
Characteristics, JTAG Interface (Test Access Port TAP)
Characteristics, Digital Inputs/Outputs
Clock Signals PIXCLK, LLC, and LLC2
Digital Video Interface
Characteristics, TTL Output Driver
TTL Output Driver Description
Timing Diagrams
Power-up Sequence
Default Wake-up Selection
Control Bus Timing Diagram
Output Enable by Pin OE
Timing of the Test Access Port TAP
Timing of all Pins connected to the Boundary-Scan-Register-Chain
Timing Diagram of the Digital Video Interface
Characteristics, Clock Signals
Control and Status Registers
Overview
Description of I
2
C Control and Status Registers
Description of FP Control and Status Registers
4
Micronas
MICRONAS [ MICRONAS ]
