VPC 323xD, VPC 324xD
ADVANCE INFORMATION
write address point
disable
disable
disable
N+1
N+2
N+3
N+4
N+5
N+6
N+8
N
N+7
N+9
N+10
N+11
SWCK
FFWE
FFIE
N+1
N+2
N+7
N+8
D0-D11
Fig. 4–15: Field memory write cycle timing
read address point
disable
disable
disable
N+1
N+2
N+3
N+4
N+5
N+6
N+8
N
N+7
N+9
N+10
N+11
SRCK
FFRE
FFOE
Hi-z
Hi-z
Hi-z
N+1
N+2
N+7
N+8
D0-D11
Fig. 4–16: Field memory read cycle timing
68
Micronas