ADVANCE INFORMATION
VPC 323xD, VPC 324xD
FP Sub-
address
Function
Default
Name
h’14e
Status of automatic standard recognition
0
ASR_STATUS
VWINERR
DISABLED
BUSY
bit[0]
bit[1]
bit[2]
bit[3]
1
1
1
1
error of the vertical standard (neither 50 nor 60 Hz)
detected standard is disabled
search active
search terminated, but failed
FAILED
bit[3:0] 0000 all ok
0001 search not started, because vwin error detected
(no input or SECAM L)
0010 search not started, because detected vert. standard
not enabled
x1x0 search started and still active
1x00 search failed (found standard not correct)
1x10 search failed, (detected color standard not enabled)
h’21
Input select:
writing to this register will also initialize the standard
INSEL
VIS
bit[1:0]
luma selector
VIN3
VIN2
VIN1
VIN4
0
00
01
10
11
bit[2]
chroma selector
1
0
CIS
IFC
0/1 VIN1/CIN
IF compensation
off
bit[4:3]
00
01
10
11
6 dB/Okt
12 dB/Okt
10 dB/MHz only for SECAM
bit[6:5]
chroma bandwidth selector
2
CBW
00
01
10
11
narrow
normal
broad
wide
bit[7]
bit[8]
bit[10:9]
0/1 adaptive/fixed SECAM notch filter
0/1 enable luma lowpass filter
hpll speed
0
0
3
FNTCH
LOWP
HPLLMD
00
01
10
11
no change
terrestrial
vcr
mixed
bit[11]
status bit, write 0, this bit is set to 1 to indicate
operation complete.
h’22
h’23
h’29
picture start position: This register sets the start point of active video
and can be used e.g. for panning. The setting is updated when ‘sdt’
register is updated or when the scaler mode register ‘scmode’ is writ-
ten.
0
0
0
SFIF
luma/chroma delay adjust. The setting is updated when ‘sdt’ register
is updated.
LDLY
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks, allowed range is +1 ... –7
helper delay register (PAL+ mode only)
bit[11:0] delay adjust for helper lines adjustable from
–96...96, 1 step corresponds to 1/32 clock
HLP_DLY
Micronas
41
MICRONAS [ MICRONAS ]
