VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 3–2: Control Registers of the Fast Processor
– default values are initialized at reset
– * indicates: register is initialized according to the current standard when SDT register is changed.
FP Sub-
address
Function
Default
Name
Standard Selection
h’20
Standard select:
SDT
bit[2:0] standard
0
0
1
2
3
4
5
6
7
PAL B,G,H,I
(50 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
3.579545
PAL
NTSC M
SECAM
NTSC44
PAL M
PAL N
PAL 60
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
NTSC
SECAM
NTSC44
PALM
PALN
PAL60
NTSCC
NTSC COMB (60 Hz)
bit[3]
0/1 MOD standard modifier
PAL modified to simple PAL
0
SDTMOD
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
bit[4]
bit[5]
bit[6]
0/1 PAL+ mode off/on
0
0
0
PALPLUS
COMB
0/1 4-H COMB mode
0/1 S-VHS mode:
SVHS
The S-VHS/COMB bits allow the following modes:
composite input signal
comb filter active
S-VHS input signal
CVBS mode (composite input signal, no luma notch)
00
01
10
11
Option bits allow to suppress parts of the initialization; this can be
used for color standard search:
bit[7]
bit[8]
bit[9]
bit[10]
no hpll setup
no vertical setup
no acc setup
0
SDTOPT
4-H comb filter setup only
bit[11]
status bit, normally write 0. After the FP has switched to a
new standard, this bit is set to 1 to indicate operation
complete. Standard is automatically initialized when the
insel register is written.
h’148
Enable automatic standard recognition
0
ASR_ENABLE
bit[0]
bit[1]
bit[2]
bit[3]
bit[4]
bit[5]
bit[6]
0/1 PAL B,G,H,I
0/1 NTSC M
0/1 SECAM
0/1 NTSC44
0/1 PAL M
(50 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
0/1 PAL N
0/1 PAL 60
0: disable recognition; 1: enable recognition
40
Micronas
MICRONAS [ MICRONAS ]
