VDP 31xxB
PRELIMINARY DATA SHEET
3. Serial Interface
3.2. Control and Status Registers
Table 3–1 gives definitions of the VDP control and status
registers. The number of bits indicated for each register
in the table is the number of bits implemented in hard-
ware, i.e. a 9-bit register must always be accessed using
two data bytes but the 7 MSB will be ‘don’t care’ on write
operations and ‘0’ on read operations. Write registers
that can be read back are indicated in Table 3–1.
2
3.1. I C-Bus Interface
Communication between the VDP and the external con-
2
2
troller is done via I C-bus. The VDP has two I C-bus
slave interfaces (for compatibility with VPC/DDP ap-
plications) – one in the front-end and one in the back-
end. Both I C-bus interfaces use I C clock synchroniza-
tion to slow down the interface if required. Both I C-bus
interfaces use one level of subaddress: the I C-bus chip
address is used to address the IC and a subaddress se-
lects one of the internal registers. The I C-bus chip ad-
dresses are given below:
2
2
2
Functions implemented by software in the on-chip con-
trol microprocessor (FP) are explained in Table 3–3.
2
2
A hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of regis-
ters with the default values given in Table 3–1.
Chip
Address
A6
A5
A4
A3
A2
A1
A0
R/W
The register modes given in Table 3–1 are
– w:
write only register
front-end
back-end
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1/0
1/0
– w/r: write/read data register
– r:
read data from VDP
– v:
register is latched with vertical sync
The registers of the VDP have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
– h:
register is latched with horizontal sync
The mnemonics used in the Micronas VDP demo soft-
ware are given in the last column.
2
Figure 3–1 shows I C-bus protocols for read and write
operations of the interface; the read operation requires
anextrastartconditionandrepetitionofthechipaddress
with read command set.
2
I C write access
subaddress 7c
S
S
1000 111
1000 111
W
W
Ack
Ack
0111 1100
0111 1100
Ack 1 or 2 byte Data Ack
P
2
I C read access
Ack
S
1000 111
R
Ack
high byte Data
low byte Data
Ack
Nak
subaddress 7c
P
W
R
Ack
Nak
S
=
=
=
=
=
=
0
1
0
1
Start
Stop
1
0
SDA
SCL
S
P
P
2
Fig. 3–1: I C-bus protocols
30
Micronas
MICRONAS [ MICRONAS ]
