VDP 313xY
ADVANCE INFORMATION
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
10
8
w/r
Sync Output
bit[5:0]
reserved (set to 0)
bit[7:6]
function of CSY pin
0
0
CSYM
00
composite sync signal output
25 Hz output (field1/field2 signal)
horizontal sync signal output
1 MHz horizontal drive clock
01
10
11
Ports
34
16
w/r
IO Port
bit[6:0]
bit[7]
IOPORT
IODATA
data to/from PORT[6:0]
reserved (set to 0)
bit[14:8]
port direction
IODIR
0
1
switch PORT[bit−8] to input
switch PORT[bit−8] to output
bit[15]
reserved (set to 0)
Hardware ID
9F
16
r
Hardware version number
read
only
HWID
bit[7:0]
hardware id (A3 = 13, B1 = 21 a.s.o.)
bit[15:8] product code VDP 31xx Y
(e.g. 32 for VDP 3132 Y)
40
Micronas
MICRONAS [ MICRONAS ]
