VDP 31xxB
PRELIMINARY DATA SHEET
4.6.4.7. Analog Front-End and ADCs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
V
VRT
Reference Voltage Top
VRT
2.5
2.6
2.8
V
10 mF/10 nF, 1 GW Probe
Luma – Path
R
C
Input Resistance
VIN1
VIN2
VIN3
VIN4
1
MW
Code Clamp – DAC = 0
VIN
VIN
VIN
VIN
Input Capacitance
4.5
pF
V
V
Full Scale Input Voltage
Full Scale Input Voltage
AGC Step Width
1.8
0.5
2.0
2.2
0.7
V
PP
V
PP
min. AGC Gain
0.6
max. AGC Gain
AGC
DNL
0.166
dB
LSB
V
6-Bit Resolution = 64 Steps
f
sig
= 1 MHz,
–2 dBr of max. AGC-Gain
AGC Differential Non-Linearity
Input Clamping Level, CVBS
±0.5
AGC
VINCL
V
1.0
1.0
Binary Level = 64 LSB
min. AGC Gain
Q
Clamping DAC Resolution
–16
15
steps
mA
5 Bit – I-DAC, bipolar
CL
V
VIN
= 1.5 V
I
Input Clamping Current per Step
0.7
1.3
±0.5
CL–LSB
DNL
Clamping DAC Differential Non-
Linearity
LSB
ICL
C
Clamping-Capacity
220
2.0
–
nF
Coupling-Cap. @ Inputs
ICL
Chroma – Path
R
Input Resistance
SVHS Chroma
CIN
VIN1
1.4
2.6
kW
CIN
V
V
Full Scale Input Voltage, Chroma
1.08
1.2
1.5
1.32
V
V
CIN
PP
Input Bias Level,
SVHS Chroma
–
–
CINDC
Binary Code for Open
Chroma Input
128
Dynamic Characteristics for all Video Paths (Luma + Chroma)
BW
Bandwidth
VIN1
VIN2
VIN3
VIN4
CIN
10
12.5
–56
50
MHz
dB
–2 dBr input signal level
1 MHz, –2 dBr signal level
XTALK
THD
Crosstalk, any Two Video Inputs
Total Harmonic Distortion
dB
1 MHz, 5 harmonics,
–2 dBr signal level
SINAD
Signal to Noise and Distortion
Ratio
45
dB
1 MHz, all outputs,
–2 dBr signal level
INL
DNL
DG
DP
Integral Non-Linearity,
Differential Non-Linearity
Differential Gain
±1
LSB
LSB
%
Code Density,
DC-ramp
±0.8
±3
–12 dBr, 4.4 MHz signal on DC-
ramp
Differential Phase
1.5
deg
58
Micronas
MICRONAS [ MICRONAS ]
