VDP 31xxB
PRELIMINARY DATA SHEET
4.6.4.1. 5 MHz Clock Output
Symbol
Parameter
Pin Name
Min.
–
Typ.
–
Max.
0.4
Unit
Test Conditions
I = 0.4 mA
OL
V
V
Output Low Voltage
Output High Voltage
Output Transition Time
CLK5
V
OL
4.0
–
–
VSTDBY
–
V
–I = 0.9 mA
OL
OH
t
50
ns
C
= 30 pF
LOAD
OT
4.6.4.2. 20 MHz Clock Input/Output, External Clock Input (XTAL1) (see Fig. 4–22)
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
V
DCAV
DC Average
CLK20
V
SUP
/2
V
SUP
/2
V
SUP/
2
V
C
= 30 pF
LOAD
– 0.3
+ 0.3
V
V
Peak to Peak
1.3
–
1.6
–
–
V
C
C
= 30 pF
= 30 pF
PP
OUT
LOAD
LOAD
t
Output Transition Time
Input Trigger Level
18
2.9
24
3.5
2.5
ns
V
OT
V
f
2.1
10
1.0
0.8
2.5
20.25
–
only for test purposes
IT
FMain Clock Frequency
FMain Clock Input DC Voltage
XTAL 1
MHz
V
F
V
V
F
MIDC
FM Clock Input AC Voltage
(p–p)
–
V
F
MIAC
t
FM Clock Input High/Low Ratio
0.9
–
1.0
–
1.1
F
MIH
t
F
MIL
t
F
FM Clock Input High to Low
Transition Time
0.15
f
MIHL
F
M
t
F
FM Clock Input Low to High
Transition Time
–
–
0.15
f
MILH
F
M
t
F
t
F
t
F
t
F
MI
MILH
MIHL
MIH
L
V
F
MIDC
V
F
MIAC
0 V
DVSS
Fig. 4–22: Main clock input
4.6.4.3. Reset Input, Test Input
Symbol
Parameter
Pin Name
Min.
–
Typ.
Max.
1.5
–
Unit
V
Test Conditions
V
IL
Input Low Voltage
Input High Voltage
RESQ
TEST
–
–
V
IH
3.0
V
56
Micronas
MICRONAS [ MICRONAS ]
