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VCT38XXA 参数 Datasheet PDF下载

VCT38XXA图片预览
型号: VCT38XXA
PDF下载: 下载PDF文件 查看货源
内容描述: 视频/控制/图文电视IC系列 [Video/Controller/Teletext IC Family]
分类和应用: 电视
文件页数/大小: 172 页 / 2222 K
品牌: MICRONAS [ MICRONAS ]
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ADVANCE INFORMATION  
VCT 38xxA  
5.8. Memory Banking  
Banking  
Register  
*D0 ... D7  
A15 ... A19  
A15 ... A19  
Interrupt  
Controller,  
DMA  
Address  
Decoder,  
Memory,  
I/O  
65C02  
Logic  
*A15  
A0 ... A14  
A0 ... A14  
*A0 ... A14  
*Processor internal Bus  
Fig. 5–5: Block diagram of Memory Banking  
The 8-bit processor W65C02 only allows access to  
64 kByte of memory space. To allow access to the  
expanded memory range above 64 kByte, a specific  
banking hardware is implemented. The physical  
address range above 32 kBytes (A15 = 1) is separated  
into several banks of which only one at a time is  
enabled and selected by the Banking register (BR),  
which is programmable as any other standard periph-  
eral register by writing the desired value into its spe-  
cific address. The content of the BR is also readable,  
so the software may check the current bank at any  
time. The applied software is responsible to program  
the BR with the correct bank number at the right time.  
Since the upper 32 kBytes range is switched immedi-  
ately after programming the BR, correct function is not  
guaranteed if it is changed by a program sequence  
running in a switched bank. BR settings need to be  
done in the lower 32 kBytes (A15 = 0), which is the  
non-switchable master bank (bank 0).  
5.8.1. Banking Register  
37: 1F0F  
38: BR  
39: Banking Register  
bit  
7
6
0
5
0
4
0
3
2
BN  
0
1
0
1
r/w  
reset  
0
0
0
BN  
r/w:  
Bank Number  
number of 32 kByte memory bank  
Setting BN = 0 should be avoided because it will mirror  
the non-switchable master bank (bank 0) into the  
upper 32-kByte area (A15 = 1). RAM, I/O pages and  
reserved addresses may be manipulated unintention-  
ally.  
RESET initializes BN = 1 to read control byte and reset  
vector from bank 1. Also, interrupt vectors have to  
reside in bank 1, because the Interrupt Controller gen-  
erates the appropriate address of bank 1, but it does  
not change the contents of the BR. Interrupt functions  
have to reside in the non-switchable master bank  
(bank 0). Otherwise,they need to be in each used  
bank, because after getting the vector the unchanged  
contents of the BR determine the current bank which is  
valid if A15 is “1”.  
Micronas  
95  
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