VCT 38xxA
ADVANCE INFORMATION
Voltage
Supervision
RC.VSI
RC.TPUI
RC.ALI
VSUPD
VREFA
Bandgap
VREFR
VREFPOR
RESET
Interrupt
Source
TPU
Watchdog
>1
+
-
VREFA
internal Reset to DMA, TPU, VDP
+
-
VREFR
RESQ
CPU Reset
>1
RC.RESDIS
>1
RC.RESOUT
Watchdog
>1
S Q
R
VREFPOR
VSUPS
+
-
>1
&
RC
Clock
Supervision
Reset
Control
CSW0.CSA
reset
>1
Reset extension
16 or 4096
oscillator pulses
&
Fig. 5–3: Block diagram of reset logic
5.7.3.1. Supply Supervision
An internal bandgap reference voltage is compared to
VSUPS. A VSUPS level below the Supply Supervision
threshold VREFPOR will permanently pull the pin
RESQ low and thus hold the VCT 38xxA in reset state
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
5.7.3.2. Clock Supervision
The Clock Supervision monitors the CPU clock fre-
quency fCPU. A frequency level below the clock super-
vision threshold of approx. 200 kHz will permanently
pull the pin RESQ low and thus hold the IC in reset
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
A frequency exceeding the specified clock frequency is
not detected.
92
Micronas
MICRONAS [ MICRONAS ]
