VCT 38xxA
ADVANCE INFORMATION
6.4. Pin Descriptions for PMQFP128 package
Pin 124, WE1Q − Write Enable Output 1 (Fig. 6–30)
This pin controls the direction of data exchange
between the CCU and the external program memory
device.
Pins 1, 4−15, 18−22, 128, ADB0−ADB18 − Address
Bus Output (Fig. 6–30)
These 19 lines provide the CCU address bus output to
access external memory.
Pin 125, WE2Q − Write Enable Output 2 (Fig. 6–30)
This pin controls the direction of data exchange
between the CCU and external the teletext page mem-
ory device.
Pin 2, 16, VSUPADB* − Supply Voltage, Address Bus
Driver
This pin is used as supply for the address bus driver.
Pin 126, OE1Q − Output Enable Output 1 (Fig. 6–30)
This pin is used to enable the output driver of the exter-
nal program memory device for read access.
Pin 3, 17, GNDADB* − Ground, Address Bus Driver
This is the ground reference for the address bus driver.
Pins 23−26, 29−32, DB0−DB7 − Data Bus Input/Out-
put (Fig. 6–31)
These 8 lines provide the bidirectional CCU data bus
to access external memory.
Pin 127, OE2Q − Output Enable Output 1 (Fig. 6–30)
This pin is used to enable the output driver of the exter-
nal teletext page memory device for read access.
Pin 27, VSUPDB* − Supply Voltage, Data Bus Driver
This pin is used as supply for the CCU data bus driver.
* Application Note:
All ground pins should be connected to one low-resis-
tive ground plane. All supply pins should be connected
separately with short and low-resistive lines to the
power supply. Decoupling capacitors from VSUPxx to
GNDxx are recommended as closely as possible to
these pins. Decoupling of VSUPD and GNDD is most
important. We recommend using more than one
capacitor. By choosing different values, the frequency
range of active decoupling can be extended.
Pin 28, GNDDB* − Ground, Data Bus Driver
This is the ground reference for the CCU data bus
driver.
Pin 55, DISINTROM − Disable Internal ROM Input
(Fig. 6–6)
A high level at this pin disables the internal CCU pro-
gram memory during reset. In this case the CCU loads
the control word from external address location
h’FFF9.
Pin 56−59, P27−P24 − I/O Port (Fig. 6–28)
These pins provide CCU controlled I/O ports.
Pin 60, VSUPP2* − Supply Voltage, Port 2 Driver
This pin is used as supply for the I/O port 2 driver.
Pin 61, GNDP2* − Ground, Port 2 Driver
This is the ground reference for the I/O port 2 driver.
Pins 66−74, VBCLK, VB0−VB7 − Digital Video Bus
Input (Fig. 6–32)
In future versions of VCT 38xxA these pins will provide
the ITU−R 656 video interface. As long as the ITU-R
656 video interface is not available, these pins have to
be connected to GNDD.
Pin 75, CLK20 − Main Clock Output (Fig. 6–9)
This is the 20.25 MHz main clock output.
Pin 79−82, 85−88, P37−P30 − I/O Port (Fig. 6–28)
These pins provide CCU controlled I/O ports.
Pin 83, VSUPP3* − Supply Voltage, Port 3Driver
This pin is used as supply for the I/O port 3 driver.
Pin 84, GNDP3* − Ground, Port 3Driver
This is the ground reference for the I/O port 3 driver.
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Micronas
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