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VCT3804A 参数 Datasheet PDF下载

VCT3804A图片预览
型号: VCT3804A
PDF下载: 下载PDF文件 查看货源
内容描述: 视频/控制/图文电视IC系列 [Video/Controller/Teletext IC Family]
分类和应用: 电视
文件页数/大小: 172 页 / 2219 K
品牌: MICRONAS [ MICRONAS ]
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ADVANCE INFORMATION  
VCT 38xxA  
FP Sub-  
address  
Function  
Default  
Name  
h’14e  
Status of automatic standard recognition  
0
ASR_STATUS  
VWINERR  
DISABLED  
BUSY  
FAILED  
NOCOLOR  
SWITCH  
bit[0]  
bit[1]  
bit[2]  
bit[3]  
bit[4]  
bit[5]  
1
1
1
1
1
1
error of the vertical standard (neither 50 nor 60 Hz)  
detected standard is disabled  
search active  
search terminated, but failed  
no color found  
standard has been switched (since last reset of this  
flag with bit[11] of asr_enable)  
bit[4:0] 00000 all ok  
00001 search not started, because vwin error detected  
(no input or SECAM L)  
00010 search not started, because detected vert. standard  
not enabled  
0x1x0 search started and still active  
01x00 search failed (found standard not correct)  
01x10 search failed, (detected color standard not enabled)  
10000 no color found (monochrome input or switch betw.  
CVBS/SVHS necessary)  
h’21  
Input select:  
bit[1:0]  
writing to this register will also initialize the standard  
luma selector  
INSEL  
00 VIN1  
00 VIS  
01 VIN2  
10 VIN3  
11 VIN4  
bit[2]  
chroma selector  
CIN1  
CIN2  
0
1
0
CIS  
bit[4:3]  
IF compensation  
00 off  
00 IFC  
01 6 dB/Okt  
10 12 dB/Okt  
11 10 dB/MHz only for SECAM  
chroma bandwidth selector  
00 narrow  
bit[6:5]  
01 CBW  
01 normal  
10 broad  
11 wide  
bit[7]  
bit[8]  
bit[10:9]  
0/1 adaptive/fixed SECAM notch filter  
0/1 enable luma lowpass filter  
hpll speed  
FNTCH  
LOWP  
00 no change  
HPLLMD  
01 terrestrial  
10 vcr  
11 mixed  
bit[11]  
status bit, write 0, this bit is set to 1 to indicate  
operation complete.  
h’22  
h’23  
Available for versions with panorama scaler only!  
0
0
SFIF  
picture start position, this register sets the start point of active video,  
this can be used e.g. for panning. The setting is updated when ’sdt’  
register is updated.  
luma/chroma delay adjust. The setting is updated when ’sdt’ register is  
updated.  
LDLY  
bit[5:0]  
reserved, set to zero  
bit[11:6]  
luma delay in clocks, allowed range is +1 ... 7  
Micronas  
41  
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