ADVANCE INFORMATION
VCT 38xxA
2
I C Sub
Number
Mode
Function
Default Name
address of bits
h’57
9
w v
end of horizontal blanking
48 HBSO
bit [8:0]
0..511
PLL2/3 filter coefficients, 1of5 bit code (n+ set bit number)
h’62
h’66
h’6a
9
9
9
w v
w v
w v
bit [5:0]
bit [5:0]
bit [5:0]
proportional coefficient PLL3, 2−n−1
proportional coefficient PLL2, 2−n−1
integral coefficient PLL2, 2−n−5
2 PKP3
1 PKP2
2 PKI2
h’15
16
w/r
horizontal drive and vertical signal control register
HVC
bit [5:0]
0..63
horizontal drive pulse duration in µs
(internally limited to 4..61)
disable/enable horizontal PLL2 and PLL3
1: disable horizontal drive pulse during
flyback
32 HDRV
bit [6]
bit [7]
0/1
0/1
0 EHPLL
0 EFLB
bit [8]
bit [9]
bit [10]
reserved, set to ’0’
enable/disable ultra black blanking
0: all outputs blanked
0
0/1
0/1
0 DUBL
1 EBL
1: normal mode
bit [11]
bit [12]
0/1
0/1
0/1
0/1
enable/disable clamping for analog RGB
input
disable/enable vertical free running mode
(FIELD is set to field2, no interlace)
enable/disable vertical protection
reserved, set to ’0’
0 DCRGB
0 SELFT
bit [13]
bit [14]
bit [15]
0 DVPR
0
1 DISKA
disable/enable phase shift of display clock
h’9d
h’32
8
8
w/r
w/r
sync output control
0 SYCTRL
INTLCINV
bit [0]
bit [4:1]
bit [5]
invert INTLC
reserved, set to ’0’
force INTLC to polarity defined in ‘INTLCINV’
INTLCFO
Miscellaneous
Fast-Blank interface mode
0 FBMOD
FBFOH
bit [0]
0
internal Fast-Blank from FBLIN pin
force internal Fast-Blank signal to High
internal Fast-Blank active High/Low
disable/enable clamping reference for
RGB outputs
1
bit [1]
bit [2]
0/1
0/1
FBPOL
CLMPR
bit [3]
1
full line MADC measurement window,
disables bit [3] in address h’25
horizontal flyback input active High/Low
reserved (set to 0)
FLMW
FLPOL
VOS
bit [4]
bit [6:5]
bit [7]
0/1
vertical output select
0
1
VERTQ output
INTLC output
h’4b
9
w v
Fast-Blank input, priority mask register
bit [7:0] 0/1 disable/enable analog Fast-Blank input
0 PBFB 1)
Micronas
39
MICRONAS [ MICRONAS ]
