ADVANCE INFORMATION
VCT 38xxA
Table 5–26: I/O Register Map
Addr.
1F6C
1F6D
1F6E
1F6F
1F70
1F71
1F72
1F73
1F7C
1F7D
1F14
1E70
1F90
1F91
1F92
1F93
1F94
1F95
1F96
1F97
1F98
1F99
1F9A
1F9B
1F9C
1F9E
1F9F
1F9D
1FFB
1FFC
1FFD
1FFE
1FFF
Mnemonic Name
CAPCOM 0 Mode Register
Mode Reset Section
CC0M
CC0I
CC0L
CC0H
CC1M
CC1I
CC1L
CC1H
CCCL
CCCH
CCCS
CCIMUX
P1D
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r
00
00
FF
FF
00
00
FF
FF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
73
03
00
00
00
00
00
00
Capture Compare Mod-
ule (CAPCOM) (chapter
5.14. on page 115)
CAPCOM 0 Interrupt Register
CAPCOM 0 Capture/Compare Low Byte
CAPCOM 0 Capture/Compare High Byte
CAPCOM 1 Mode Register
CAPCOM 1 Interrupt Register
CAPCOM 1 Capture/Compare Low Byte
CAPCOM 1 Capture/Compare High Byte
CAPCOM Counter Low Byte
CAPCOM Counter High Byte
CAPCOM Clock Select
CAPCOM Input Multiplex Register
Port 1 Data Register
r
w
w
r/w
w
Ports (chapter 5.18. on
page 126)
P1O
Port 1 Output Register
Port 1 Mode Register
P1M
w
P1E
Port 1 Enable Register
Port 2 Data Register
w
P2D
r/w
w
P2O
Port 2 Output Register
Port 2 Mode Register
P2M
w
P2E
Port 2 Enable Register
Port 3 Data Register
w
P3D
r/w
w
P3O
Port 3 Output Register
Port 3 Mode Register
P3M
w
P3E
Port 3 Enable Register
Port 4 Data Register
w
P4D
r/w
w
P4M
Port 4 Mode Register
P4E
Port 4 Enable Register
CLK20 Mode Register
w
C20M
TST5
TST4
TST3
TST1
TST2
w
Test Register 5
r
Test Registers (chapter
5.6. on page 90)
Test Register 4
w
Test Register 3
w
Test Register 1
w
Test Register 2
w
Micronas
135
MICRONAS [ MICRONAS ]
