VCT 38xxA
ADVANCE INFORMATION
5.17.3.Measurement Errors
The result of the conversion mirrors the voltage poten-
tial of the sampling capacitance (typically 15 pF) at the
end of the sampling time. This capacitance has to be
charged by the source through the source impedance
within the sampling time period. To avoid measure-
ment errors, system design has to make sure that at
the end of the sampling period, the potential error on
the sampling capacitance is less than ±0.1 LSB.
Measurement errors may occur, when the voltage of
high-impedance sources has to be measured:
– To reduce these errors, the sampling time may be
increased by programming the field TSAMP in regis-
ter AD1.
– In cases where high-impedance sources are only
rarely sampled, a 100-nF capacitor from the input to
GNDS is a sufficient measure to ensure that the
potential on the sampling capacitance reaches the
full source potential, even with the shortest sampling
time.
– In some high-impedance applications a charge
pumping effect may influence the measurement
result when two sources are measured alternatingly.
5.17.4.Comparator
In addition to the A/D converter the module contains a
comparator. The level at the A/D converter input is
compared to VSUPS/2. The state of the comparator
output can be read at flag CMPO in register AD0.
The interrupt source output of this module is routed to
the Interrupt Controller logic. The CMPO interrupt
source is gated with an internal clock. This is the rea-
son why interrupts are generated as long as the level
at the comparator is lower than the internal reference.
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Micronas
MICRONAS [ MICRONAS ]
