VCT 38xxA
ADVANCE INFORMATION
5.19.I/O Register Cross Reference
Table 5–26: I/O Register Map
Addr.
1E00
1E01
1E02
1E03
1E04
1E05
1E06
1E07
1E08
1E09
1E0A
1E0B
1E0C
1E0D
1E0E
1E0F
1E10
1E11
1E12
1E13
1E14
1E15
1E16
1E17
1E18
1E64
1E65
1E66
1E67
1E68
1E69
Mnemonic Name
Mask 1 Low Byte
Mode Reset Section
MASK1L
MASK2L
MASK3L
MASK4L
MASK1H
MASK2H
MASK3H
MASK4H
CMP1L
CMP2L
CMP3L
CMP4L
CMP1H
CMP2H
CMP3H
CMP4H
MAP1L
MAP2L
MAP3L
MAP4L
MAP1H
MAP2H
MAP3H
MAP4H
DMAIM
PAR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
00
FF
FF
FF
00
00
00
DMA Interface (chapter
5.9. on page 96)
Mask 2 Low Byte
Mask 3 Low Byte
Mask 4 Low Byte
Mask 1 High Byte
Mask 2 High Byte
Mask 3 High Byte
Mask 4 High Byte
Compare 1 Low Byte
Compare 2 Low Byte
Compare 3 Low Byte
Compare 4 Low Byte
Compare 1 High Byte
Compare 2 High Byte
Compare 3 High Byte
Compare 4 High Byte
Map 1 Low Byte
Map 2 Low Byte
Map 3 Low Byte
Map 4 Low Byte
Map 1 High Byte
Map 2 High Byte
Map 3 High Byte
Map 4 High Byte
DMA Interface Mode
Patch Address Register 0
Patch Address Register 1
Patch Address Register 2
Patch Data Register
Patch Enable Register 0
Patch Enable Register 1
Memory Patch Module
(chapter 5.11. on
page 107)
PAR1
PAR2
PDR
PER0
PER1
132
Micronas
MICRONAS [ MICRONAS ]
