VCT 38xxA
ADVANCE INFORMATION
5.18.2.2. Universal Port Mode
286: 1F90
289: 1F94
292: 1F98
287: P1D
290: P2D
293: P3D
288: Port 1 Data Register
291: Port 2 Data Register
294: Port 3 Data Register
Each port bit can be individually configured to several
port modes. The output driver of each pin has to be
enabled by setting the EN flag. Using the OUT flag the
output stage can be configured to either open drain or
push pull output. The MOD flag selects the source of
the output value.
bit
7
D7
0
6
D6
0
5
4
D4
0
3
D3
0
2
D2
0
1
D1
0
0
D0
0
r/w
D5
reset
0
D0−7
r:
w:
Universal Port Data Input/Output
Read pin level resp. data latch.
Write data to data latch.
Table 5–25: Port mode register settings
Mode
MOD EN
D
Function
To use a port pin as software output, the appropriate
driver must be activated by setting the EN flag and the
MOD flag must be programmed to Normal mode.
Normal
Input
x
0
1
x
READ of register
PxD returns port
pin input levels to
data bus.
295: 1F91
298: 1F95
301: 1F99
296: P1O
299: P2O
302: P3O
297: Port 1 Output Register
300: Port 2 Output Register
303: Port 3 Output Register
Normal
Output
0
Data WRITE to register
PxD changes level
of port pin output
drivers.
bit
7
OUT7
0
6
5
OUT5
0
4
OUT4
0
3
OUT3
0
2
OUT2
0
1
OUT1
0
0
OUT0
0
w
OUT6
READ of register
PxD returns the
PxD register set-
ting to the data
bus.
reset
0
OUT0−7
w1:
w0:
Output Flag
Output driver is open drain
Output driver is push pull
Special
Input
x
x
x
x
Port pin input level
is presented to
special hardware.
304: 1F92
307: 1F96
310: 1F9A
305: P1M
308: P2M
311: P3M
306: Port 1 Mode Register
309: Port 2 Mode Register
312: Port 3 Mode Register
Special
Output
1
1
Special hardware
drives port pin.
bit
w
7
6
5
MOD5
0
4
MOD4
0
3
MOD3
0
2
MOD2
0
1
MOD1
0
0
MOD0
0
READ of register
PxD returns port
pin input levels to
data bus.
MOD7
MOD6
reset
0
0
MOD0−7
w1:
Normal/Special Mode Flag
Special Output Mode
w0:
Normal Output Mode
The Special Input mode is always active. This allows
manipulating the input signal to the special hardware
through Normal Output operations by software.
The MOD flag defines from which source the pin is
driven if the EN flag is true.
As the Special Output mode allows reading the pin lev-
els, the output state of the special hardware may be
read by the CPU.
313: 1F93
316: 1F97
319: 1F9B
314: P1E
317: P2E
320: P3E
315: Port 1 Enable Register
318: Port 2 Enable Register
321: Port 3 Enable Register
5.18.3.Universal Port Registers
bit
7
EN7
0
6
5
EN5
0
4
EN4
0
3
EN3
0
2
EN2
0
1
EN1
0
0
EN0
0
w
EN6
Universal Port Data registers PxD contain input/output
data of the corresponding port. The “x” in PxD means
the number of the port. Thus PxD stands for P1D to
P3D.
reset
0
EN0−7
w1:
w0:
Enable Flag
Output driver is enabled
Output driver is disabled
128
Micronas
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