ADVANCE INFORMATION
VCT 38xxA
5.17.A/D Converter (ADC)
5.17.1.Features
– A/D converter with 10-bit resolution.
– Successive approximation, charge balance type.
– Input multiplexer with 15 analog channels.
– Sample and hold circuit.
This 10-bit analog to digital converter allows the con-
version of an analog voltage in the range of 0 to URef
into a digital value. A multiplexer connects the ADC to
one of 15 analog input ports. A sample-and-hold circuit
holds the analog voltage during conversion. The dura-
tion of the sampling time is programmable. The A/D
conversion is done by a charge balance A/D converter
using successive approximation.
– 4/8/16/32 µs conversion selectable for optimum
throughput/accuracy balance.
– Zero standby current, 300 µA active current.
SR1.ADC
0
VSUPS
1
4
GNDS
A
10
15
P10-17
P20-26
MUX
S&H
D
2
AD1
AD0
w
r
TSAMP
CHANNEL
x x
r
x
x
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
EOC
CMPO
CMPO
Interrupt
Source
Fig. 5–4: Block Diagram of the ADC
5.17.2.Operation
After reset, the module is off (zero standby current).
The module is enabled by the flag SR1.ADC. The user
must ensure that the flag End of Conversion (EOC) in
register AD0 is true, before he starts to operate the
module.
A write access to register AD0 indicating sample time
and channel number starts the conversion. The flag
EOC signalizes the end of conversion. The 10-bit
result is stored in the registers AD1 (8 MSB) and AD0.
The conversion rate depends on the software, the
oscillator frequency and the programmed sample time.
The ADC module is not affected by CPU Slow mode.
Micronas
123
MICRONAS [ MICRONAS ]
