VCT 38xxA
ADVANCE INFORMATION
5.15.Pulse Width Modulator
5.15.1.Features
– 8-bit resolution
– standby mode
Each of the 4 available PWMs is an 8-bit reload down-
counter with fixed reload interval. It serves to generate
a frequency signal with variable pulse width or, with an
external low-pass filter, as a digital to analog converter.
PWMx
x: PWM number 0 to 3
y: Standby Register 0 or 2
w
Pulse Width Register
8
0
load
clk
fOSC/29
fOSC/21
1
0
1
1
S
R
Q
PWMx
zero
8 bit down counter
0
SRy.PWMx
Fig. 5–1: Block diagram of 8-bit PWM
5.15.2.General
Returning a PWM to standby mode by resetting its
respective enable flag will immediately set its output
Low.
A PWM’s 8-bit down-counter is clocked by its input
clock and counts down to zero. Reaching zero, it stops
and sets the output to Low. A load pulse reloads the
counter with the content of the PWM register, restarts
it and sets the output to High. The repetition rate is
19.775 KHz, the reload period is 50.57 µs.
The state of the down-counters is not readable.
5.15.5.PWM Registers
The PWMs are not affected by CPU Slow mode. It is
recommended that the CPU should not write the PWM
registers during Slow mode.
262: 1F50
265: 1F51
268: 1F52
271: 1F53
263: PWM0
266: PWM1
269: PWM2
272: PWM3
264: PWM 0 Register
267: PWM 1 Register
270: PWM 2 Register
273: PWM 3 Register
5.15.3.Initialization
bit
7
6
5
4
3
2
1
0
0
w
Pulse width value
Prior to entering active mode, proper SW initialization
of the Ports assigned to function as PWMx outputs has
to be made. The ports have to be configured Special
Out (see Section 5.18. on page 126).
reset
0
0
0
0
0
0
0
Table 5–19: Pulse Width Programming
5.15.4.Operation
After reset, all PWMs are in standby mode (inactive)
and the output signal PWMx is Low.
Pulse width value Pulse duty factor
00h
01h
02h
:
0% (Output is static Low)
For entering active mode, the enable bit in the corre-
sponding standby register has to be set (see Section
5.5. on page 89). The desired pulse width value is then
written into register PWMx. Each PWM will start pro-
ducing its output signal immediately after the next sub-
sequent load pulse.
1/256
2/256
:
FEh
FFh
254/256
During active mode, a new pulse width value is set by
simply writing to the register PWMx. Upon the next
subsequent load pulse the PWM will start producing
an output signal with the new pulse width value, start-
ing with a High level.
100% (Output is static High) 1)
1) Pulse duty factor 255/256 is not selectable.
120
Micronas
MICRONAS [ MICRONAS ]
