TPU 3035, TPU 3040
PRELIMINARY DATA SHEET
0282 H
0285 H
0288 H
028B H
R/W
DRAM DISPLAY POINTER HIGH
DRAM SLICER POINTER HIGH
DRAM CPU WRITE POINTER HIGH
DRAM CPU READ POINTER HIGH
Bit
Reset
–
Function
4 to 0
5 most significant bits of 21 bit address pointer
static (no autoincrement)
writing this register clears all lower bits of related pointer
028C H
R/W
Reset
–
DRAM DATA
Function
Bit
all
8 bit value
028D H
R/W
Reset
–
DRAM HAMMING DATA
Bit
all
Function
8 bit value
writing this register resets hamming decoder
028E H
Write
Reset
0
DRAM MODE
Bit
4
Function
1 = next CPU write without WEQ but with address increment
0 = normal CPU write mode
3
2
1
0
0
1
1
0
1 = reset address pointer and switch off refresh during standby
0 = keep address pointer and refresh during standby
1 = display channel enable
0 = display channel disable
1 = slicer channel enable
0 = slicer channel disable
1 = slow mode timing
0 =fast mode timing
0290 H
Bit
Write
Reset
01 H
ACQ SOFT SLICER
Function
4 to 0
5 bit binary soft slicer level is compared with ABS[data]
(*32≤data≤)31)
0291 H
0293 H
Write
ACQ TTX BITSLICER FREQUENCY LOW
ACQ VPS BITSLICER FREQUENCY LOW
Bit
all
Reset
–
Function
8 LSBs of bitslicer frequency
MICRONAS INTERMETALL
59
MICRONAS [ MICRONAS ]
