TPU 3035, TPU 3040
PRELIMINARY DATA SHEET
HSYNC
Clamping
Blanking
Fig. 2–6: Internal Timing
0253 H
Write
Reset
37 H
HALFLINE CODE
Bit
all
Function
horizontal position to reset HSYNC flip-flop in normal sync mode (in character)
horizontal position of halfline HSYNC in self-timed interlaced mode (in character)
0254 H
Write
Reset
0
DISPLAY MODE 1
Bit
7
Function
1 = OSD layer always uses FONT 1
0 = OSD layer changes from FONT 1 to FONT 2 if ASCII≥20H
6
5
1
1
0
0
1 = enable OSD layer
0 = disable OSD layer
1 = active flash phase of OSD layer
0 = inactive flash phase of OSD layer
4
1 = 13 scanlines/character
0 = 8 scanlines/character
3 to 0
With this scan line the OSD layer starts display of the first text line. By slow incrementing of this value soft
scroll begins.
0255 H
Write
Reset
1
DISPLAY MODE 2
Bit
6
Function
1 = skew delay enable
0 = skew delay disable
5
4
3
2
1
0
0
0
1
1
0
1
1 = VSYNC active high
0 = VSYNC active low
1 = HSYNC active high
0 = HSYNC active low
1 = 10.125MHz display clock
0 = 20.25MHz display clock
1 = font pointer offset 10 scanlines/character
0 = font pointer offset 8 or 16 scanlines/character (depending on bit 1)
1 = font pointer offset 16 scanlines/character
0 = font pointer offset 8 scanlines/character
1 = 10 scanlines/character
0 = 8 or 13 scanlines/character (depending on bit 4 in register 0254 H)
54
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
