TPU 3035, TPU 3040
PRELIMINARY DATA SHEET
0213 H
Write
Reset
0
INTERFACE MODE
Bit
2
Function
1 = IIM Bus test enable (if normal test mode)
0 = IIM Bus test disable
1
0
0
1
1 = standby enable
0 = standby disable
(if bit 2 of register 0202H = 1)
1 = IIC Bus
0 = IIM Bus
0220 H
R/W
Reset
FF H
INTERRUPT SOURCE
Bit
all
Function
write: 1 = reset interrupt source
0 = no action
read: 1 = pending interrupt
0 = no pending interrupt
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
IR input falling edge
IR input rising edge
timer
12
(bit 2 from timer = every 3.24ms)
vertical sync display
slave interface
(bus write of address or read/write of data register)
master interface
TTX acquisition start
TTX acquisition stop
0221 H
Write
Reset
3B H
INTERRUPT ENABLE
Bit
all
Function
for bit mapping see register 0220 H
1 = interrupt enable
0 = interrupt disable
0222 H
Write
Reset
1
INTERRUPT & TIMER MODE
Bit
3
Function
1 = timer not latched by falling edge of IR input (see Fig. 2–5)
0 = timer latched by falling edge of IR input
2
1
0
1
1
1
1 = timer not latched by rising edge of IR input (see Fig. 2–5)
0 = timer latched by rising edge of IR input
1 = IRQ generated by falling edge of IR input
0 = NMI generated by falling edge of IR input
1 = IRQ generated by rising edge of IR input
0 = NMI generated by rising edge of IR input
52
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
