TPU 3035, TPU 3040
PRELIMINARY DATA SHEET
4.10. Memory Manager
4.11. Memory Organization
The Memory manager is the core of the internal TPU
3040 software. Most of the acquisition and display
related functions are controlled by this management.
The upper end of the memory is defined by the DRAM
size, the lower end can be defined with the
PAGE_MEMORY command. Default memory organisa-
tion is shown in Fig. 4–8.
20 00 00 = 16Mbit
DRAM
08 00 00 = 4Mbit
02 00 00 = 1Mbit
Page Memory
n x 1 KByte
00 80 00 = 256Kbit
Acquisition
00 40 00
Display Bank
Scratch
Memory
4 KByte
00 30 00
TTX Display Bank
Page
Table
Memory
Manager
Page
Memory
4 KByte
00 20 00
Acquisition
Scratch
Display
Memory
4 KByte
00 10 00
Page Table
Display
Controller
4 KByte
00 00 00
Fig. 4–7: Memory Manager
Fig. 4–8: Memory Organization
44
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
