SDA9410
Preliminary Data Sheet
I²C Bus
Sub address 53
Bit
Name
Function
D2
SLAVEON Reading Data of Slave Channel
1: enabled (slave picture is displayed)
0: disabled
D1
D0
MEMRDM Memory Read Mode Master Channel (SRC-Mode)
1:reading only 1 field memory area for AABB conversion
0:reading both field memory areas for ABAB conversion
MEMRDS Memory Read Mode Slave Channel (SRC-Mode)
1:reading data in SSC-configuration, 1 or 2 decimated fields,
AABB
0:reading data in PIP-configuration (joint line free, ABAB)
Sub address 54
Bit Name
Function
D7...D0 VPAN
Vertical Panning
-line number indicating the start line of reading for the master
channel
-defines the displayed part of the picture with activated vertical
interpolation
[VPAN=0]
Sub address 55
Bit
Name
Function
D7
REFRON Refresh On
1: memory refresh activated
0: no memory refresh
D6
RSHFTM Joint Line Free Display of Master Channel by Shifting the
Output Raster Phase (SSC-Mode): Should be set in all
operation modes to 1
1: enabled
0: disabled
158
Micronas
MICRONAS [ MICRONAS ]
