SDA9410
5.12.5
Preliminary Data Sheet
Display processing
Coarse delay
Before Digital-to-Analog conversion an adjustment of the phase of the luminance signal
can be performed (I²C Bus parameter COARSDEL, 5Ch). The delay of the luminance
can be varied by periods (-8, ...[1]... , +7) of the DAC clock (2*CLKD). This can be used
to compensate different delay times of external analog filters.
I²C Bus
Sub address
Description
parameter
COARSDEL
5Ch
Delay of the luminance signal in relation to the chrominance signal
in 2*CLKD clocks
Table 99
5.12.6
Output write I²C Bus parameter
Digital-to-Analog conversion
Three 9-bit Digital-to-Analog converters are implemented. The DACs are short-circuit
protected converters with current outputs. The full range output current of the IY_O,
IU_O, IV_O channels (IOFR) is determined by the current IREF at the pin RREF_I by IOFR
~ 10 IREF . The voltage at the pin RREF_I is generated via pin UREF_I by an internal
operational amplifier and follows the voltage at the pin UREF_I. Thus IREF is given by IREF
~ VUREF/RREF where RREF is a resistor between RREF_I and analog ground. Another way
to define IREF is the application of a current sink at the RREF_I point. For recommended
values of VUREF and IREF compare "Operating range" on page 171. For applications
with lower requirements there is still another way to define IOFR: Connect pin UREF_I to
the positive supply and apply a resistor against ground. Since in this operation mode the
internal reference amplifier reaches saturation, the exact value of IREF is not exactly
predictable.
I²C Bus
Sub address
Description
parameter
CHROM_AMP
5Eh
Chrominance amplification factor adjustment for DAC output
1: amplification factor 2
0: amplification factor 1
Table 100
Output write I²C Bus parameter
116
Micronas
MICRONAS [ MICRONAS ]
