SDA9410
Preliminary Data Sheet
Display processing
I²C Bus
Sub address
Description
parameter
VERINT
VPAN
47h
54h
Vertical expansion factor for master channel
Vertical adjustment of the output picture for master channel
Table 87
5.12
Output write I²C Bus parameter
Display processing
Signals
IY_O
Pin number
Description
87
84
90
Analog Y (luminance) output signal
Analog U (chrominance) output signal
Analog V (chrominance) output signal
IU_O
IV_O
Table 88
Output signals
The display processing part contains an integrated triple 9-bit DAC and performs digital
enhancements and manipulations of the digital video component signal. The figure
below shows the block diagram of the display processing part and the existing I²C Bus
parameters.
27 MHz
54 MHz
YBORDERD
UBORDERD
VBORDERD
DACEN
THRESY
ASCENTLTI
BCOF HCOF
CORING
CHROM_AMP
COARSDEL
Coarse
Delay
+7/-8
9
9
9
8
8
9
9
8
9
DAC
DAC
DAC
YO
UO
VO
Delay
Peaking
Delay
DLTI
DCTI
YIN
OFC
Framing
9
9
8:8:8
Delay
9
9
8
8
CIN
4:4:4
9
9
Delay
THRESC
ASCENTCTI
Figure 52
Block diagram of display processing
109
Micronas
MICRONAS [ MICRONAS ]
