SDA 9400
5
Pin description
Pin No.
2,8,24,42,55
9,25,41,56
36,52,58
35,51,53,57,
59
43,..,50
Name
VSS1
VDD1
VSS2
VDD2
YIN0...7
Type
S
S
S
S
I/TTL
I/TTL
PD
I/TTL
Description
Supply voltage (
V
SS
= 0 V )
Supply voltage (
V
DD
= 3.3 V )
Supply voltage (
V
SS
= 0 V )
Supply voltage (
V
DD
= 3.3 V )
Data input Y (see input data format)
Data input UV (for 4:2:2 parallel, see input data format)
(for CCIR 656, see input data format)
System reset. The RESET input is low active. In order to
ensure correct operation a
"Power
On Reset" must be
performed. The RESET pulse must have a minimum
duration of two clock periods of the system clock CLK1.
H-Sync input
(only for full CCIR 656)
V-Sync input
(only for full CCIR 656)
Synchronization enable input
I
2
C-Bus data line (5V ability)
I
2
C-Bus clock line (5V ability)
System clock 1
Data output UV (see output data format)
Data output Y (see output data format)
Horizontal active video output
EXSYN=0 (I²C-bus parameter): V-Sync output
EXSYN=1: External V-Sync input for output part
EXSYN=0 (I²C-bus parameter): H-Sync output
EXSYN=1: External H-Sync input for output part
Interlace signal for AC coupled vertical deflection
Crystal connection / System clock 2
Clock output (depends on I²C parameters CLK11EN,
CLK21EN, FREQR, see also
Clock concept
on Page 37)
Test input, connect to
V
SS
for normal operation
31,..,34;37,..., UVIN0...7
40
30
RESET
23
22
29
21
20
54
17,..,10
62
61
60
18
28
27
26
19
HIN
VIN
SYNCEN
SDA
SCL
CLK1
UVOUT0...7
HREF
VOUT/
VEXT
HOUT/
HEXT
X1 / CLK2
X2
CLKOUT
TEST
I/TTL
PD
I/TTL
PD
I/TTL
I/O
I
I/TTL
O/TTL
O/TTL
O/TTL
I/O/
TTL
I/O/
TTL
7,..,3;1;64;63 YOUT0...7
INTERLACED O/TTL
I/TTL
O/TTL
I/TTL
O/ANA Crystal connection
Micronas
9
Preliminary Data Sheet
MICRONAS [ MICRONAS ]
