PRELIMINARY DATA SHEET
MSP 44x8G
Table 3–9: Write Registers on I2C Subaddress 10hex, continued
Register
Address
Function
Name
MODUS
00 30hex
MODUS Register
MODUS
General MSP 44x8G Options
bit[15]
0
undefined, must be 0
bit[14:13]
detected 4.5 MHz carrier is interpreted as:1)
standard M (Korea)
standard M (BTSC)
standard M (Japan)
Carrier at 4.5 MHz is ignored (chroma carrier)
0
1
2
3
Preference in Automatic Standard Detection:
bit[12]
detected 6.5 MHz carrier is interpreted as:1)
0
1
standard L (SECAM)
standard D/K1, D/K2, or D/K NICAM
bit[11:9]
bit[8]
0
undefined, must be 0
0/1
ANA_IN_1+/ANA_IN_2+;
select analog sound IF input pin
bit[7]
bit[6]
0/1
active/tristate state of audio clock output pin
AUD_CL_OUT
word strobe alignment (synchronous I2S)
WS changes at data word boundary
WS changes one clock cycle in advance
0
1
bit[5]
0/1
0/1
0
master/slave mode of I2S interface (must be set to 0
(= Master) in case of NICAM mode)
active/tristate state of I2S output pins
bit[4]
bit[3]
state of digital output pins D_CTR_I/O_0 and _1
active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register.
see also: MODUS[1])
1
tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
bit[2]
bit[1]
0
undefined, must be 0
0/1
disable/enable STATUS change indication by means of
the digital I/O pin D_CTR_I/O_1
Necessary condition: MODUS[3] = 0 (active)
bit[0]
0/1
off/on: Automatic Sound Select
1) Valid at the next start of Automatic Standard Detection.
Micronas
23
MICRONAS [ MICRONAS ]
