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MSP4418G 参数 Datasheet PDF下载

MSP4418G图片预览
型号: MSP4418G
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准音频处理器 [Multistandard Sound Processor]
分类和应用:
文件页数/大小: 85 页 / 653 K
品牌: MICRONAS [ MICRONAS ]
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MSP 44x8G  
PRELIMINARY DATA SHEET  
6.6. Manual Mode:  
6.7. Demodulator Source Channels in Manual Mode  
6.7.1. Terrestrial Sound Standards  
Description of DSP Read Registers  
All readable registers are 16-bit wide. Transmissions  
via I2C bus have to take place in 16-bit words. Some of  
the defined 16-bit words are divided into low and high  
byte, thus holding two different control entities.  
Table 6–11 shows the source channel assignment of  
the demodulated signals in case of manual mode for  
all terrestrial sound standards. See Table 2–2 for the  
assignment in the Automatic Sound Select mode. In  
manual mode for terrestrial sound standards, only two  
demodulator sources are defined.  
These registers are not writable.  
6.6.1. Stereo Detection Register  
for A2 Stereo Systems  
6.7.2. SAT Sound Standards  
Table 6–12 shows the source channel assignment of  
the demodulated signals for SAT sound standards.  
Stereo Detection  
Register  
00 18hex  
H
Stereo Mode  
Reading  
(two’s complement)  
MONO  
near zero  
STEREO  
positive value (ideal  
reception: 7Fhex  
)
BILINGUAL  
negative value (ideal  
reception: 80hex)  
Note: It is not necessary to read out and evaluate the  
A2 identification level. All evaluation is performed in  
the MSP and indicated in the STATUS register.  
6.6.2. DC Level Register  
DC Level Readout  
FM1 (MSP-Ch2)  
00 1Bhex  
00 1Chex  
H+L  
H+L  
DC Level Readout  
FM2 (MSP-Ch1)  
DC Level  
[8000hex ... 7FFFhex]  
values are 16 bit two’s  
complement  
The DC level register measures the DC component of  
the incoming FM signals (FM1 and FM2). This can be  
used for seek functions in satellite receivers and for IF  
FM frequencies fine tuning. If the DCO frequency is  
lower than the actuel carrier frequency, the resulting  
DC level will be positive, an dvia versa. In the audio  
signal the DC content is suppressed. The time con-  
stant τ, defining the transition time of the DC Level  
Register, is approximately 28 ms.  
80  
Micronas  
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