PRELIMINARY DATA SHEET
MSP 34x1G
3. Control Interface
response time is about 0.3 ms. If the MSP cannot
accept another byte of data (e.g. while servicing an
internal interrupt), it holds the clock line I2C_CL low to
force the transmitter into a wait state. The I2C Bus
Master must read back the clock line to detect when
the MSP is ready to receive the next I2C transmission.
The positions within a transmission where this may
happen are indicated by ’Wait’ in Section 3.1.3. The
maximum wait period of the MSP during normal opera-
tion mode is less than 1 ms.
3.1. I2C Bus Interface
The MSP 34x1G is controlled via the I2C bus slave
interface.
The IC is selected by transmitting one of the
MSP 34x1G device addresses. In order to allow up to
three MSP ICs to be connected to a single bus, an
address select pin (ADR_SEL) has been implemented.
With ADR_SEL pulled to high, low, or left open, the
MSP 34x1G responds to different device addresses. A
device address pair is defined as a write address and a
read address (see Table 3–1).
3.1.1. Internal Hardware Error Handling
In case of any hardware problems (e.g. interruption of
the power supply of the MSP), the MSP’s wait period is
extended to 1.8 ms. After this time period elapses, the
MSP releases data and clock lines.
Writing is done by sending the write device address,
followed by the subaddress byte, two address bytes,
and two data bytes.
Reading is done by sending the write device address,
followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the
addressed data is completed by sending the device
read address and reading two bytes of data.
Indication and solving the error status:
To indicate the error status, the remaining acknowl-
edge bits of the actual I2C-protocol will be left high.
Additionally, bit[14] of CONTROL is set to one. The
MSP can then be reset via the I2C bus by transmitting
the RESET condition to CONTROL.
Refer to Section 3.1.3. for the I2C bus protocol and to
Section 3.4. “Programming Tips” on page 45 for pro-
posals of MSP 34x1G I2C telegrams. See Table 3–2
for a list of available subaddresses.
Indication of reset:
Besides the possibility of hardware reset, the MSP can
also be reset by means of the RESET bit in the CON-
TROL register by the controller via I2C bus.
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I2C bus is shown in
Due to the architecture of the MSP 34x1G, the IC can-
not react immediately to an I2C request. The typical
Fig. 4–27 on page 69.
Table 3–1: I2C Bus Device Addresses
ADR_SEL
Low
High
Left Open
(connected to DVSS)
(connected to DVSUP)
Mode
Write
80hex
Read
Write
84hex
Read
Write
Read
89hex
MSP device address
81hex
85hex
88hex
Table 3–2: I2C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
0000 0000
00
Read/Write
Write: Software reset of MSP (see Table 3–3)
Read: Hardware error status of MSP
WR_DEM
RD_DEM
WR_DSP
RD_DSP
0001 0000
0001 0001
0001 0010
0001 0011
10
11
12
13
Write
Write
Write
Write
write address demodulator
read address demodulator
write address DSP
read address DSP
Micronas
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MICRONAS [ MICRONAS ]
