MSP 34x1G
PRELIMINARY DATA SHEET
2.8. I2S Bus Interface
2.9. ADR Bus Interface
The MSP 34x1G has a synchronous master/slave
input/output interface running on 32 kHz.
For the ASTRA Digital Radio System (ADR), the
MSP 3401G, MSP 3411G, and MSP 3451G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 34x1G should be provided on a
feature connector:
The interface accepts two formats:
1. I2S_WS changes at the word boundary
2. I2S_WS changes one I2S-clock period before the
word boundaries.
All I2S options are set by means of the MODUS and
the I2S_CONFIGURATION registers.
– AUD_CL_OUT
– I2S_DA_IN1 or I2S_DA_IN2
– I2S_DA_OUT
The I2S bus interface consists of five pins:
– I 2 S _ D A _ I N 1 , I 2 S _ D A _ I N 2 :
– I2S_WS
I2S serial data input: 16, 18....32 bits per sample
– I2S_CL
– I2S_DA_OUT:
I2S serial data output: 16, 18...32 bits per sample
– ADR_CL, ADR_WS, ADR_DA
– I2S_CL:
For more details, please refer to the DRP 3510A data
sheet.
I2S serial clock
– I2S_WS:
I2S word strobe signal defines the left and right
sample
2.10. Digital Control I/O Pins and
Status Change Indication
If the MSP 34x1G serves as the master on the I2S
interface, the clock and word strobe lines are driven by
the IC. In this mode, only 16 or 32 bits per sample can
be selected. In slave mode, these lines are input to the
IC and the MSP clock is synchronized to 576 times the
I2S_WS rate (32 kHz). NICAM operation is not possi-
ble in slave mode.
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 41). This enables the controlling of external
hardware switches or other devices via I2C-bus.
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 26).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 28).
An I2S timing diagram is shown in Fig. 4–28 on
page 71.
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary, I2C bus interactions are reduced to a
minimum (see STATUS register on page 28 and
MODUS register on page 26).
2.11. Clock PLL Oscillator and Crystal Specifications
The MSP 34x1G derives all internal system clocks
from the 18.432-MHz oscillator. In NICAM or in I2S-
Slave mode, the clock is phase-locked to the corre-
sponding source. Therefore, it is not possible to use
NICAM and I2S-Slave mode at the same time.
For proper performance, the MSP clock oscillator
requires a 18.432-MHz crystal. Note that for the
phase-locked modes (NICAM, I2S-Slave), crystals with
tighter tolerance are required.
16
Micronas
MICRONAS [ MICRONAS ]
