MSP 34x0G
DATA SHEET
Table 6–2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!
Demodulator
Address MSP-
Description
Page
Read Registers
(hex)
00 23
00 38
00 3E
00 57
02 1F
02 1E
Version
C_AD_BITS
ADD_BITS
CIB_BITS
3410,
3450
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits
NICAM: bit [10:3] of additional data bits
NICAM: CIB1 and CIB2 control bits
NICAM error rate, updated with 182 ms
Not for customer use
97
97
97
98
98
98
ERROR_RATE
PLL_CAPS
AGC_GAIN
Not for customer use
6.2. DSP Write and Read Registers for Manual/Compatibility Mode
Table 6–3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well
Write Register
Address Bits
(hex)
Operational Modes and Adjustable Range
Reset
Mode
Page
Volume SCART1 channel: Ctrl. mode
FM Fixed Deemphasis
00 07
00 0F
[7:0]
[15:8]
[7:0]
[7:0]
[7:0]
[7:0]
[Linear mode / logarithmic mode]
[50 µs, 75 µs, J17, OFF]
[OFF, WP1]
00
99
hex
50 µs
OFF
B/G
99
FM Adaptive Deemphasis
Identification Mode
99
00 15
00 17
00 40
[B/G, M]
100
100
99
FM DC Notch
[ON, OFF]
ON
Volume SCART2 channel: Ctrl. mode
[Linear mode / logarithmic mode]
00
hex
Table 6–4: DSP Read Registers; Subaddress: 13hex, all registers are not writable
Additional Read Registers
Address Bits
(hex)
Output Range
Page
Stereo detection register for
A2 Stereo Systems
00 18
[15:8]
[80 ... 7F
]
8 bit two’s complement
100
hex
hex
DC level readout FM1/Ch2-L
DC level readout FM2/Ch1-R
00 1B
00 1C
[15:0]
[15:0]
[8000 ... 7FFF
]
16 bit two’s complement
16 bit two’s complement
100
100
hex
hex
[8000 ... 7FFF
]
hex
hex
88
May 27, 2003; 6251-476-1DS
Micronas
MICRONAS [ MICRONAS ]
