MSP 3400C
PRELIMINARY DATA SHEET
MSP Clock Output
typ. 20 ns
at inverter output
Clock Inverter Output
Timing window
>10 ns
for the low to high edge at
pin 17 of DMA 2381 (XTAL2)
<42 ns
Fig. 10–2: Timing requirements for the clock signal at the DMA 2381 clock input
In the following table, the input/output clock-specification of the D2MAC circuit is shown.
Table 10–1: Clock input and output specification for MSPs
MSP 3400C >C6
new Version
MSP 3410/00 TC27
new Version
MSP 3410/00 TC15
actual Version
XTAL_IN min
(minimum amplitude)
>0.7 Vpp
22 pF
>0.7 Vpp
22 pF
>0.7 Vpp
31 pF
C input
(after Reset)
AUD_CL_OUT min
with C load
>1.2 Vpp
40 pF
>1.2 Vpp
40 pF
>1.0 Vpp
43 pF
Rout (HF) typ.
150 Ω
120 Ω
120 Ω
Table 10–2: Clock input and output specification for ICs connected to MSP
DMA 2381
DMA 2386
AMU2481
XTAL_IN min
>0.7 Vpp
>0.7 Vpp
>0.7 Vpp
Clock-in min
(minimal amplitude)
C input
24 pF
7pF
7pF
10 pF with: Adr.
204,14=1
For the DMA_SYNC input specification of the MSP, please refer to page 54 “V
, V
.”
DMAIL
DMAIH
66
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
