PRELIMINARY DATA SHEET
MAS 3507D
1.1. Features
– Serial asynchronous MPEG bit stream input (SDI)
– Parallel (PIO-DMA) Input
– Broadcast and multimedia operation mode
– Automatic locking to given data rate in broadcast
mode
MPEG 1/2 Layer 2/3 Audio Decoder
Release Note: Revision bars indicate significant
changes to the previous edition.
This data sheet applies to MAS 3507D version G10
and following versions.
1. Introduction
The MAS 3507D is a single-chip MPEG layer 2/3 audio
decoder for use in audio broadcast or memory-based
playback applications. Due to embedded memories,
the embedded DC/DC up-converter, and the very low
power consumption, the MAS 3507D is ideally suited
for portable electronics.
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compres-
sion rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used in DVB, ADR, and DAB) achieves a com-
pression of 8:1 providing CD quality.
In order to achieve better audio quality at low bit rates
(<64 kbit/s per audio channel), three additional sam-
pling frequencies are provided by MPEG 2
(ISO 13818-3). The MAS 3507D decodes both layer 2
and layer 3 bit streams as defined in MPEG 1 and 2.
The multichannel/multilingual capabilities defined by
MPEG 2 are not supported by the MAS 3507D. An
extension to the MPEG 2 layer 3 standard developed
by FhG Erlangen, Germany sometimes referenced as
MPEG 2.5, for extremely low bit rates at sampling fre-
quencies of 12, 11.025, or 8 kHz is also supported by
the MAS 3507D.
– Data request triggered by ’demand signal’ in multi-
media mode
– Output audio data delivered (in various formats) via
an I
2
S bus (SDO)
– Digital volume / stereo channel mixer / Bass / Treble
– Output sampling clocks are generated and con-
trolled internally.
– Ancillary data provided via I
2
C interface
– Status information accessible via PIO pins or I
2
C
– “CRC Error” and “MPEG Frame Synchronization”
Indicators at Pins in serial input mode
– Power management for reduced power consumption
at lower sampling frequencies
– Low power dissipation (30 mW @ f
s
≤
12 kHz,
46 mW @ f
s
≤
24 kHz, 86 mW @ f
s
> 24 kHz @
2.7 V)
– Supply voltage range: 1.0 V to 3.6 V due to built-in
DC/DC converter (1-cell/2-cell battery operation)
– Adjustable power supply supervision
– Power-off function
– Additional functionality achievable via download
software (CELP voice Decoder, ADPCM encoder /
decoder)
CLKI
CLKO
MAS 3507D
Clock
Synthesizer
DC/DC
Converter
/3/
decoded output
/3/
Serial Out
I
2
S
RISC DSP Core
PIO
/8+5/
MPEG 1/2
audio bit stream
/2/
Serial In
serial control
I
2
C
/2/
MPEG frame sync
CRC error
Fig. 1–1:
MAS 3507D block diagram
Micronas
5
MICRONAS [ MICRONAS ]
