MAS 3504D
2.6.5.1. Example 1:16 Bits/Sample (I2S Compatible Data Format)
A schematic timing diagram of the SDO interface in 16 bit/sample mode with delayed data by 1 clock cycle is shown
in Fig. 2–5.
Vh
SOC
Vl
Vh
7
8
9
6
5
4
3 2 1 0
15 14 13 12 11 10 9
14
15
13 12 11 10
8
7 6 5 4 3 2 1 0
SOD
SOI
Vl
Vh
Vl
right 16-bit audio sample
left 16-bit audio sample
Fig. 2–5: Schematic timing of the SDO interface in 16bit/sample mode
2.6.5.2. Example 2:32 Bit/Sample (Inverted SOI)
If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing
bits are set to zero by default (see Fig. 2–6).
Vh
...
...
SOC
Vl
Vh
Vl
SOD
SOI
... 7
31
30 29 28 27 26 25 ... 7
0
6 5 4 3 2 1 0
31 30 29 28 27 26 25
6
5
4
3
2
1
Vh
Vl
right 32-bit audio sample
left 32-bit audio sample
Fig. 2–6: Schematic timing of the SDO interface in 32 bit/sample mode
Micronas
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