MAS 3504D
2.6.3.2. End of DMA Transfer
2.6.4. Audio Input Interface (SDI)
The above procedure will be repeated until the
MAS 3504D sets the EOD signal to “0”, which indi-
cates that the transfer of one data block has been exe-
cuted. Subsequently, the controller should set PR to
“0”, wait until EOD rises again, and then repeat the
procedure ((see Section 2.6.3.1. on page 9)) to send
the next block of data. The DMA buffer is 10 bytes long
(one frame).
The A/D interface is a standard I2S interface (16/32 bit,
stereo). This input is used for G.729 recording mode
and must be slaved to the D/A output clock and word-
strobe signals.
The interface is configurable by software to work in dif-
ferent modes. It is possible to choose:
– inverted or non inverted word strobe (SOI),
– no delay or delay of data related to word strobe
– inverted or non inverted I2S-Clock (SOC).
The recommended PIO DMA conditions and the char-
acteristics of the PIO timing are given in Table 2–2.
For further details see Section 3.5.4. on page 18
Table 2–2: PIO DMA Timing
2.6.5. Audio Output Interface (SDO)
Symbol PIO Pin
Min.
0.010
40
Max.
2000
160
Unit
µs
The audio output interface of the MAS 3504D is a
standard I2S interface. As the G.729 standard is only
working on mono signals, the same signal is written to
both output channels (left and right).
tst
tr
PR, EOD
PR, RTR
ns
tpd
PR,
PI[19:12]
120
480
ns
The interface is configurable by software to work in dif-
ferent modes. It is possible to choose:
tset
th
trtrq
tpr
PI[19:12]
PI[19:12]
RTR
160
160
200
480
40
no limit
no limit
30000
no limit
no limit
160
ns
ns
ns
ns
ns
ns
µs
– 16 or 32 bit/sample modes,
– inverted or non inverted word strobe (SOI),
– no delay or delay of data related to word strobe
– inverted or non inverted I2S-clock (SOC).
PR
For further details see Section 3.5.4. on page 18
trpr
teod
teodq
PR, RTR
PR, EOD
EOD
40
2.5
500
10
Micronas
MICRONAS [ MICRONAS ]
