ADVANCE INFORMATION
DDP 3310B
4.6.4.7. Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins
Symbol
VIL
Parameter
Pin Name Min.
Typ.
Max.
0.8
−
Unit
V
Test Conditions
Input Low Voltage
Input High Voltage
Input Capacitance
HS
−
−
−
5
VS
VS2
CM0
CM1
FREQSEL
VIH
2.0
−
V
CIN
−
pF
tIS
tIH
Input Setup Time
Input Hold Time
HS
VS
VS2
6
7
−
−
−
−
ns
ns
V
IH
LLC1
V
IL
t
IH
t
IS
V
IH
HS, VS, VS2 Inputs
V
IL
Fig. 4–23: Sync Inputs referenced to line-locked clock
4.6.4.8. Horizontal Flyback Input
Symbol
VIL
Parameter
Pin Name Min.
Typ.
Max.
1.8
−
Unit
V
Test Conditions
Input Low Voltage
Input High Voltage
Input Hysteresis
HFLB
−
−
−
−
VIH
2.6
0.1
V
VIHST
−
V
4.6.4.9. FIFO Control Signals
Symbol
Parameter
Pin Name Min.
Typ.
Max.
Unit
Test Conditions
VOL
Output Low Voltage
FIFORRD
FIFORD
−
−
0.4
V
IOL = 1.6 mA
I2C[PSTSY] = 6
FIFORWR
FIFOWR
VOH
Output High Voltage
Output Transition Time
Output Current
VSUPP
− 0.4
−
VSUPP
20
V
−IOL = 1.6 mA
I2C[PSTSY] = 6
tOT
−
10
−
ns
mA
CLOAD = 30pF
I2C[PSTSY] = 6
IOL
−10
10
Micronas
49
MICRONAS [ MICRONAS ]
