256Mb and 512Mb (256Mb/256Mb), P30-65nm
Configuration Register
Latency Count
The latency count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-
mine this value. The First Access Latency Count figure shows the data output latency for
different LC settings.
Figure 13: First Access Latency Count
CLK [C]
Valid
Address [A]
Address
ADV# [V]
Code 0 (Reserved
)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQ[15:0] [D/Q]
Output
Output
Output
Output
Output
Output
Output
Output
Code
1
(Reserved)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
Output
Output
Output
Output
Output
Output
Output
Code
2
Valid
Valid
Valid
Valid
Valid
Valid
Output
Output
Output
Output
Output
Output
Code
Code
Code
Code
Code
3
4
5
6
7
Valid
Valid
Valid
Valid
Valid
Output
Output
Output
Output
Output
Valid
Valid
Valid
Valid
Output
Output
Output
Output
Valid
Valid
Valid
Output
Output
Output
Valid
Valid
Output
Output
Valid
Output
1. First Access Latency Count Calculation:
Note:
• 1 / CLK frequency = CLK period (ns)
• n x (CLK period) ≥ tAVQV (ns) – tCHQV (ns)
• Latency Count = n
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
47
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