256Mb and 512Mb (256Mb/256Mb), P30-65nm
Status Register
sequence error occurs during an ERASE SUSPEND, the status register contains the com-
mand sequence error status (SR[7,5,4] set). When the ERASE operation resumes and fin-
ishes, possible errors during the operation cannot be detected via the status register be-
cause it contains the previous error status.
3. When bits 5:4 indicate a PROGRAM/ERASE operation error, either a CLEAR STATUS REG-
ISTER 50h) or a RESET command must be issued with a 15µs delay.
Clear Status Register
The CLEAR STATUS REGISTER command clears the status register. It functions inde-
pendently of VPP. The device sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without
clearing them. The status register should be cleared before starting a command se-
quence to avoid any ambiguity. A device reset also clears the status register.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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