P30-65nm
1.3
Virtual Chip Enable Description (2-Gbit)
The P30-65nm device employs a Virtual Chip Enable to combine two 1-Gbit dies with a
common chip enable, CE#, for Easy BGA packages. Address A27 is then used to select
between the die pair with CE# asserted. When chip enable is asserted and A27 is low
(VIL), the lower flash die is selected; when chip enable is asserted and A27 is high (VIH),
the upper flash die is selected.
Table 1:
Flash Die Virtual Chip Enable Truth Table for 2-Gbit (1-Gbit/1-Gbit) Devices
Die Selected
CE#
A27
Lower Flash Die
Upper Flash Die
L
L
L
H
Datasheet
6
Sept 2012
Order Number: 208042-06