P30-65nm
In asynchronous page mode, sixteen data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the address bus is driven onto DQ[15:0] after
the initial access delay. The lowest four address bits determine which word of the
16-word page is output from the data buffer at any given time.
Refer to Figure 20, “Asynchronous Page-Mode Read Timing for Easy BGA” on page 53
for more detailed information.
Note:
If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level,
WAIT signal can be floated and ADV# must be tied to ground.
5.3
Read - Synchronous Mode (Easy BGA)
To perform a synchronous burst read on array or non-array, an initial address is driven
onto the address bus, and CE# is asserted. WE# and RST# must already have been
deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately,
ADV# can remain asserted throughout the burst access, in which case the address is
latched on the next valid CLK edge while ADV# is asserted. Once OE# is asserted, the
the first word is driven onto DQ[15:0] on the next valid CLK edge after initial access
latency delay (see Section 11.2.2, “Latency Count (RCR[14:11])” on page 36).
Subsequent data is output on valid CLK edges following a minimum delay tCHQV (see
Table 25, “AC Read Specifications -” on page 51).
However, for a synchronous non-array read, the same word of data will be output on
successive clock edges until the burst length requirements are satisfied.
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus. When
the device is operating in synchronous non-array read mode, such as read status, read
ID, or read query, the WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
Refer to the following waveforms for more detailed information: Figure 21,
“Synchronous Single-Word Array or Non-array Read Timing for Easy BGA” on page 54,
and Figure 22, “Continuous Burst Read, showing an Output Delay Timing for Easy BGA”
on page 54, and Figure 23, “Synchronous Burst-Mode Four-Word Read Timing for Easy
BGA” on page 55.
5.4
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 7, “Command Bus Cycles” on page 21
shows the bus cycle sequence for each of the supported device commands, while
Table 6, “Command Codes and Definitions” on page 19 describes each command. See
Table 26, “AC Write Specifications” on page 55 for signal-timing details.
When the device is operating in write operations, WAIT is set to a deasserted state as
determined by RCR.10.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
Datasheet
17
Sept 2012
OrderNumber:208042-06
MICRON [ MICRON TECHNOLOGY ]
