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PC28F00AP30TF 参数 Datasheet PDF下载

PC28F00AP30TF图片预览
型号: PC28F00AP30TF
PDF下载: 下载PDF文件 查看货源
内容描述: 美光并行NOR闪存的嵌入式存储器( P30-65nm ) [Micron Parallel NOR Flash Embedded Memory (P30-65nm)]
分类和应用: 闪存存储
文件页数/大小: 92 页 / 1225 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, 1Gb, 2Gb: P30-65nm  
Features  
List of Figures  
Figure 1: Easy BGA Block Diagram ................................................................................................................... 8  
Figure 2: Memory Map – 512Mb and 1Gb ......................................................................................................... 9  
Figure 3: Memory Map – 2Gb ......................................................................................................................... 10  
Figure 4: 56-Pin TSOP – 14mm x 20mm .......................................................................................................... 11  
Figure 5: 64-Ball Easy BGA – 8mm x 10mm x 1.2mm ....................................................................................... 12  
Figure 6: 56-Lead TSOP Pinout – 512Mb and 1Gb ........................................................................................... 13  
Figure 7: 64-Ball Easy BGA (Top View – Balls Down) – 512Mb, 1Gb, and 2Gb .................................................... 14  
Figure 8: Example VPP Supply Connections .................................................................................................... 31  
Figure 9: Block Locking State Diagram ........................................................................................................... 35  
Figure 10: First Access Latency Count ............................................................................................................ 40  
Figure 11: Example Latency Count Setting Using Code 3 ................................................................................. 41  
Figure 12: End of Wordline Timing Diagram ................................................................................................... 41  
Figure 13: OTP Register Map .......................................................................................................................... 46  
Figure 14: Word Program Procedure ............................................................................................................... 62  
Figure 15: Buffer Program Procedure .............................................................................................................. 63  
Figure 16: Buffered Enhanced Factory Programming (BEFP) Procedure ........................................................... 64  
Figure 17: Block Erase Procedure ................................................................................................................... 65  
Figure 18: Program Suspend/Resume Procedure ............................................................................................ 66  
Figure 19: Erase Suspend/Resume Procedure ................................................................................................. 67  
Figure 20: Block Lock Operations Procedure ................................................................................................... 68  
Figure 21: OTP Register Programming Procedure ............................................................................................ 69  
Figure 22: Status Register Procedure .............................................................................................................. 70  
Figure 23: Reset Operation Waveforms ........................................................................................................... 72  
Figure 24: AC Input/Output Reference Timing ................................................................................................ 76  
Figure 25: Transient Equivalent Load Circuit .................................................................................................. 76  
Figure 26: Clock Input AC Waveform .............................................................................................................. 76  
Figure 27: Asynchronous Single-Word Read (ADV# LOW) ................................................................................ 80  
Figure 28: Asynchronous Single-Word Read (ADV# Latch) ............................................................................... 80  
Figure 29: Asynchronous Page Mode Read ...................................................................................................... 81  
Figure 30: Synchronous Single-Word Array or Nonarray Read .......................................................................... 82  
Figure 31: Continuous Burst Read with Output Delay ..................................................................................... 83  
Figure 32: Synchronous Burst Mode 4-Word Read ........................................................................................... 84  
Figure 33: Write to Write Timing .................................................................................................................... 87  
Figure 34: Asynchronous Read to Write Timing ............................................................................................... 87  
Figure 35: Write to Asynchronous Read Timing ............................................................................................... 88  
Figure 36: Synchronous Read to Write Timing ................................................................................................ 89  
Figure 37: Write to Synchronous Read Timing ................................................................................................ 90  
PDF: 09005aef845667b3  
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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