512Mb, Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Nonvolatile and Volatile Configuration Registers
Table 10: Nonvolatile Configuration Register Bit Definitions
Note 1 applies to entire table
Bit Name
Settings
Description
Notes
15:12 Number of
0000 (identical to 1111)
Sets the number of dummy clock cycles subse-
quent to all FAST READ commands.
The default setting targets the maximum al-
lowed frequency and guarantees backward com-
patibility.
2, 3
dummy clock 0001
cycles
0010
.
.
1101
1110
1111
11:9 XIP mode at 000 = XIP: Fast Read
Enables the device to operate in the selected XIP
mode immediately after power-on reset.
power-on re- 001 = XIP: Dual Output Fast Read
set
010 = XIP: Dual I/O Fast Read
011 = XIP: Quad Output Fast Read
100 = XIP: Quad I/O Fast Read
101 = Reserved
110 = Reserved
111 = Disabled (Default)
8:6 Output driver 000 = Reserved
Optimizes impedance at VCC/2 output voltage.
strength
001 = 90 Ohms
010 = 60 Ohms
011 = 45 Ohms
100 = Reserved
101 = 20 Ohms
110 = 15 Ohms
111 = 30 (Default)
5
4
Reserved
X
"Don't Care."
Reset/hold
0 = Disabled
Enables or disables hold or reset.
1 = Enabled (Default)
(Available on dedicated part numbers.)
3
2
1
0
Quad I/O pro- 0 = Enabled
tocol 1 = Disabled (Default, Extended SPI pro-
tocol)
Dual I/O pro- 0 = Enabled
Enables or disables quad I/O protocol.
4
4
Enables or disables dual I/O protocol.
tocol
1 = Disabled (Default, Extended SPI pro-
tocol)
128Mb seg-
ment select
0 = Upper 128Mb segment
1 = Lower 128Mb segment (Default)
Selects a 128Mb segment as default for 3B ad-
dress operations. See also the extended address
register.
Address bytes 0 = Enable 4B address
1 = Enable 3B address (Default)
Defines the number of address bytes for a com-
mand.
1. Settings determine device memory configuration after power-on. The device ships from
the factory with all bits erased to 1 (FFFFh). The register is read from or written to by
READ NONVOLATILE CONFIGURATION REGISTER or WRITE NONVOLATILE CONFIGURA-
TION REGISTER commands, respectively.
Notes:
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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