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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第1页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第2页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第3页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第5页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第6页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第7页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第8页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第9页  
64Mb: x4, x8, x16 SDRAM  
Features  
List of Figures  
Figure 1: 16 Meg x 4 Functional Block Diagram ................................................................................................. 8  
Figure 2: 8 Meg x 8 Functional Block Diagram ................................................................................................... 9  
Figure 3: 4 Meg x 16 Functional Block Diagram ............................................................................................... 10  
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11  
Figure 5: 54-Ball VFBGA x16 (Top View) ......................................................................................................... 12  
Figure 6: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 14  
Figure 7: 54-Ball VFBGA (8mm x 8mm) – Package Codes F4/B4 ....................................................................... 15  
Figure 8: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 17  
Figure 9: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) .............................................. 18  
Figure 10: ACTIVE Command ........................................................................................................................ 29  
Figure 11: READ Command ........................................................................................................................... 30  
Figure 12: WRITE Command ......................................................................................................................... 31  
Figure 13: PRECHARGE Command ................................................................................................................ 32  
Figure 14: Initialize and Load Mode Register .................................................................................................. 40  
Figure 15: Mode Register Definition ............................................................................................................... 42  
Figure 16: CAS Latency .................................................................................................................................. 45  
t
Figure 17: Example: Meeting tRCD (MIN) When 2 < RCD (MIN)/tCK < 3 .......................................................... 46  
Figure 18: Consecutive READ Bursts .............................................................................................................. 48  
Figure 19: Random READ Accesses ................................................................................................................ 49  
Figure 20: READ-to-WRITE ............................................................................................................................ 50  
Figure 21: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 51  
Figure 22: READ-to-PRECHARGE .................................................................................................................. 51  
Figure 23: Terminating a READ Burst ............................................................................................................. 52  
Figure 24: Alternating Bank Read Accesses ..................................................................................................... 53  
Figure 25: READ Continuous Page Burst ......................................................................................................... 54  
Figure 26: READ – DQM Operation ................................................................................................................ 55  
Figure 27: WRITE Burst ................................................................................................................................. 56  
Figure 28: WRITE-to-WRITE .......................................................................................................................... 57  
Figure 29: Random WRITE Cycles .................................................................................................................. 58  
Figure 30: WRITE-to-READ ............................................................................................................................ 58  
Figure 31: WRITE-to-PRECHARGE ................................................................................................................. 59  
Figure 32: Terminating a WRITE Burst ............................................................................................................ 60  
Figure 33: Alternating Bank Write Accesses ..................................................................................................... 61  
Figure 34: WRITE – Continuous Page Burst ..................................................................................................... 62  
Figure 35: WRITE – DQM Operation ............................................................................................................... 63  
Figure 36: READ With Auto Precharge Interrupted by a READ ......................................................................... 65  
Figure 37: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 66  
Figure 38: READ With Auto Precharge ............................................................................................................ 67  
Figure 39: READ Without Auto Precharge ....................................................................................................... 68  
Figure 40: Single READ With Auto Precharge .................................................................................................. 69  
Figure 41: Single READ Without Auto Precharge ............................................................................................. 70  
Figure 42: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 71  
Figure 43: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 71  
Figure 44: WRITE With Auto Precharge ........................................................................................................... 72  
Figure 45: WRITE Without Auto Precharge ..................................................................................................... 73  
Figure 46: Single WRITE With Auto Precharge ................................................................................................. 74  
Figure 47: Single WRITE Without Auto Precharge ............................................................................................ 75  
Figure 48: Auto Refresh Mode ........................................................................................................................ 77  
Figure 49: Self Refresh Mode .......................................................................................................................... 79  
Figure 50: Power-Down Mode ........................................................................................................................ 80  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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