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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Features  
SDR SDRAM  
MT48LC16M4A2 – 4 Meg x 4 x 4 Banks  
MT48LC8M8A2 – 2 Meg x 8 x 4 Banks  
MT48LC4M16A2 – 1 Meg x 16 x 4 Banks  
Options  
Marking  
Features  
• PC100- and PC133-compliant  
• Fully synchronous; all signals registered on positive  
edge of system clock  
• Internal, pipelined operation; column address can  
be changed every clock cycle  
• Internal banks for hiding row access/precharge  
• Programmable burst lengths: 1, 2, 4, 8, or full-page  
• Auto precharge, includes concurrent auto precharge  
and auto refresh modes  
• Self refresh modes: standard and low-power  
(not available on AT devices)  
• Auto refresh  
– 64ms, 4096-cycle refresh  
(commercial and industrial)  
– 16ms, 4096-cycle refresh  
tWR = 2 CLK  
A2  
• Plastic package – OCPL1  
– 54-pin TSOP II (400 mil)  
– 54-pin TSOP II (400 mil) Pb-free  
– 54-ball VFBGA (x16 only) (8mm x  
8mm)  
– 54-ball VFBGA (x16 only) (8mm x  
8mm)  
• Timing – cycle time  
– 6ns @ CL = 3 (x16 only)  
– 6ns @ CL = 3  
– 7.5ns @ CL = 3 (PC133)  
– 7.5ns @ CL = 2 (PC133)  
• Self refresh  
– Standard  
– Low-power  
TG  
P
F4  
B42  
-63  
-6A  
-753  
-7E  
None  
L3  
(automotive)  
LVTTL-compatible inputs and outputs  
• Single 3.3V ±0.3V power supply  
• Operating temperature range  
– Commercial (0˚C to +70˚C)  
– Industrial (–40˚C to +85˚C)  
– Automotive (–40˚C to +105˚C)  
• Revision  
None  
IT  
AT2  
Options  
• Configuration  
– 16 Meg x 4 (4 Meg x 4 x 4 banks)  
– 8 Meg x 8 (2 Meg x 8 x 4 banks)  
– 4 Meg x 16 (1 Meg x 16 x 4 banks)  
• Write recovery (tWR)  
Marking  
:G, :J  
16M43  
8M8  
4M16  
1. Off-center parting line.  
Notes:  
2. Contact Micron for availability.  
3. Available only on Revision G.  
Table 1: Key Timing Parameters  
CL = CAS (READ) latency  
Clock  
Frequency (MHz)  
Speed Grade  
Target tRCD-tRP-CL  
tRCD (ns)  
tRP (ns)  
CL (ns)  
18  
-6  
167  
167  
133  
133  
3-3-3  
3-3-3  
3-3-3  
2-2-2  
18  
18  
20  
15  
18  
18  
20  
15  
-6A  
-75  
-7E  
18  
20  
15  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
© 1999 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.