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MT48LC16M8A2FC-8ELIT 参数 Datasheet PDF下载

MT48LC16M8A2FC-8ELIT图片预览
型号: MT48LC16M8A2FC-8ELIT
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 内存集成电路动态存储器时钟
文件页数/大小: 59 页 / 1835 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb: x4, x8, x16  
SDRAM  
PRECHARGE command is that it requires that the com-  
mand and address buses be available at the appropriate  
time to issue the command; the advantage of the  
PRECHARGE command is that it can be used to truncate  
fixed-length or full-page bursts.  
Full-page READ bursts can be truncated with the  
BURST TERMINATE command, and fixed-length READ  
burstsmaybetruncatedwithaBURSTTERMINATEcom-  
mand, provided that auto precharge was not activated.  
The BURST TERMINATE command should be issued x  
cycles before the clock edge at which the last desired data  
element is valid, where x equals the CAS latency minus  
one. This is shown in Figure 12 for each possible CAS  
latency; data element n + 3 is the last desired data ele-  
ment of a longer burst.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
BURST  
TERMINATE  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
COMMAND  
ADDRESS  
DQ  
X = 1 cycle  
BANK,  
COL n  
D
OUT  
D
n + 1  
OUT  
DOUT  
DOUT  
n + 3  
n
n + 2  
CAS Latency = 2  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
ADDRESS  
DQ  
BURST  
TERMINATE  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
X = 2 cycles  
BANK,  
COL n  
D
OUT  
DOUT  
D
n + 2  
OUT  
DOUT  
n + 3  
n
n + 1  
CAS Latency = 3  
NOTE:  
DQM is LOW.  
DONT CARE  
Figure 12  
Terminating a READ Burst  
128Mb: x4, x8, x16 SDRAM  
128MSDRAM_E.p65 Rev. E; Pub. 1/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2001, Micron Technology, Inc.  
21  
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