128Mb: x4, x8, x16
SDRAM
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
Starting Column Order of Accesses Within a Burst
Address
Type = Sequential Type = Interleaved
A0
0
1
0-1
1-0
0-1
1-0
2
4
A1 A0
A11
A8
A6 A5 A4
A1
Address Bus
A10
A7
A3 A2
A0
A9
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
11
9
8
6
5
4
1
10
7
3
2
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst Length
A2 A1 A0
*Should program
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
M11, M10 = “0, 0”
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
8
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Full
Page
(y)
n = A0-A11/9/8
(location 0-y)
Not Supported
Cn…
Burst Type
M3
0
Sequential
Interleaved
NOTE: 1. For full-page accesses: y = 2,048 (x4), y = 1,024
(x8), y = 512 (x16).
1
2. For a burst length of two, A1-A9, A11 (x4), A1-A9
(x8) or A1-A8 (x16) select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A9, A11 (x4), A2-A9
(x8) or A2-A8 (x16) select the block-of-four burst;
A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A9, A11 (x4), A3-
A9 (x8) or A3-A8 (x16) select the block-of-eight
burst; A0-A2 select the starting column within the
block.
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
5. For a full-page burst, the full row is selected and
A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select
the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9, A11 (x4), A0-A9
(x8) or A0-A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
Figure 1
Mode Register Definition
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
10
MICRON [ MICRON TECHNOLOGY ]
